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出版社：電子工業出版社 ISBN：9787121398704 商品編碼：10024916312582 品牌：文軒 出版時間：2020-11-01 代碼：129 作者：維克多·P.納爾遜等
" 作 者:(美)維克多·P.納爾遜 等 著  定 價:129 出 版 社:電子工業出版社 出版日期:2020年11月01日 頁 數:624 裝 幀:平裝 ISBN:9787121398704  內容待完善  ●0ComputersandDigitalSystemsbrLearningObjectivesbr0ABriefHistoryofComputingbr0BeginningsMechanicalComputers2br02EarlyElectronicComputers2br03TheFirstFourGenerationsofComputers2br04TheFifthGenerationandBeyond4br02DigitalSystems4br02DigitalversusAnalogSystems5br022DigitalSystemLevelsofAbstraction5br03ElectronicTechnologies8br03Moore’sLaw9br032FixedversusProgrammableLogic0br033Microcontrollers0br034DesignEvolution0br04ApplicationsofDigitalSystems2br04GeneralPurposeDigitalComputers2br042Controllers7br043InternetofThingsIoT8br044Interfacing8br05SummaryandReviewQuestions20br06CollaborationActivities20brReferences2brNumberSystemsandDigitalCodes22brLearningObjectives22brNumberSystems22br itionalandPolynomialNotations23br2CommonlyUsedNumberSystems23br2Arithmetic24br2BinaryArithmetic24br22HexadecimalArithmetic27br3BaseConversions29br3ConversionMethodsandAlgorithms29br32ConversionbetweenBaseAandBaseBWhenB=Ak32br4SignedNumberRepresentation33br4SignMagnitudeNumbers33br42ComplementaryNumberSystems35br5DigitalCodes45br5NumericCodes46br52CharacterandOtherCodes50br53ErrorDetectionandCorrectionCodes53br6SummaryandReviewQuestions58br7CollaborationActivities58brProblems59br2LogicCircuitsandBooleanAlgebra6brLearningObjectives6br2LogicGatesandLogicCircuits6br2TruthTables6br22BasicLogicGates62br23CombinationalLogicCircuits65br24SequentialLogicCircuits68br22HardwareDescriptionLanguagesHDLs69br22Verilog69br222VHDL70br23BooleanAlgebra72br23 tulatesandFundamentalTheorems72br232BooleanLogicFunctionsandEquations77br233MintermsMaxtermsandCanonicalForms78br234IncompletelySpecifiedFunctionsDon’tCares8br24MinimizationofLogicExpressions82br24MinimizationGoalsandMethods82br242KarnaughMapsKMaps84br243MinimizationofLogicExpressionsUsingKMaps9br244QuineMcCluskeyMethod06br25SummaryandReviewQuestionsbr26CollaborationActivities2brProblems3br3CombinationalLogicCircuitDesignandAnalysis23brLearningObjectives23br3DesignofCombinationalLogicCircuits23br3ANDORandNANDNANDCircuits24br32ORANDandNORNORCircuits25br33TwoLevelCircuits26br34 ltilevelCircuitsandFactoring28br35EXCLUSIVEORXORCircuits3br32AnalysisofCombinationalCircuits34br32BooleanAlgebra34br322TruthTables36br323TimingDiagrams37br324 itiveandNegativeLogic42br33DesignUsingHigherLevelDevices43br33Decoders43br332Encoders55br333 ltiplexersandDemultiplexers59br334ArithmeticCircuits69br34SummativeDesignExamples82br34DesignFlow82br342BankSecurityLockController82br343SevenSegmentDisplayDecoder86br344FourFunctionArithmeticLogicUnitaddsubtractANDXOR92br345BinaryArray ltiplier96br35SummaryandReviewQuestions200br36CollaborationActivities20brProblems202br4IntroductiontoSequentialCircuits23brLearningObjectives23br4ModelsandClassesofSequentialCircuits24br4FiniteStateMachines24br42StateDiagramsandStateTables26br43AlgorithmicStateMachines29br42MemoryDevices22br42Latches222br422FlipFlops234br423LatchandFlipFlopSummary244br43Registers244br44ShiftRegisters248br45Counters253br45SynchronousBinaryCounters254br452AsynchronousBinaryCounters257br453ModuloNCounters258br454RingandTwistedRingCounters263br46SummativeDesignExamples272br46RegisterFile272br462 ltiphaseClock273br463DigitalTimer275br464ProgrammableBaudRateGenerator278br47SummaryandReviewQuestions28brReferences28br48CollaborationActivities282brProblems283br5SynchronousSequentialLogicCircuitAnalysisandDesign29brLearningObjectives29br5AnalysisofSequentialCircuits29br5CircuitAnalysisUsingStateDiagramsandStateTables29br52AnalysisofSequentialCircuitLogicDiagrams293br53Summary305br52DesignofSynchronousSequentialCircuits305br52DesignProcedure306br522FlipFlopInputTables309br523DesignExamples3br524OneHotFiniteStateMachineDesignMethod33br525IncompletelySpecifiedSequentialCircuits336br53StateReductioninSequentialCircuits338br53RedundantStates338br532StateReductioninCompletelySpecifiedCircuits340br54SummativeDesignExamples344br54DrinkVendingMachineControlUnit344br542Binary ltiplier347br543TrafficLightController350br55SummaryandReviewQuestions36brReferences362br56CollaborationActivities362brProblems366br6AsynchronousSequentialCircuitAnalysisandDesign377brLearningObjectives377br6TypesofAsynchronousCircuits377br62AnalysisandDesignofPulseModeCircuits378br62AnalysisofPulseModeCircuits379br622DesignofPulseModeCircuits384br63AnalysisofFundamentalModeCircuits390br63Introduction392br632ExcitationandFlowTables393br633AnalysisProcedure394br64DesignofFundamentalModeCircuits396br64FlowTableDesignandRealization396br642RacesandCycles405br643EliminatingRaceConditions409br644Hazards48br65SummativeDesignExamples49br65DesignFlow49br652AsynchronousVendingMachineController420br653AsynchronousBusArbiters422br66SummaryandReviewQuestions429br67CollaborationActivities429brProblems430br7ProgrammableDigitalLogicDevices440brLearningObjectives440br7ProgrammableDigitalLogicDeviceTechnology440br72FieldProgrammableGateArraysFPGAs442br72ConfigurableLogicBlocks443br722InputOutputBlocks452br723InterconnectResources454br724ClockResources456br725OtherFPGAResourcesandOptions457br726FPGADesignProcessandExamples457br73ProgrammableLogicDevicesPLDs466br73ArrayStructuresforCombinationalLogicFunctions467br732PLDOutputandFeedbackOptions484br733PLDsforSequentialCircuitApplications4br734ComplexPLDsCPLDs492br735DesignExamples493br74SummativeDesignExamples496br74BinaryDivisionCircuit496br742 ltiplexedSevenSegmentDisplayController502br75SummaryandReviewQuestions50brReferences50br76CollaborationActivities5brProblems53br8DesignofDigitalSystems59brLearningObjectives59br8DesignProcesses59br8HierarchicalDesign59br82FixedLogicversusProgrammableLogic52br83DigitalSystemDesignFlow52br82DesignExamples52br82TinyRISC4TRISC4Processor522br822OneLaneTrafficController533br823UniversalAsynchronousReceiverTransmitterUART540br824ElevatorController547br83SummaryandReviewQuestions552br84CollaborationActivities552brProblems552brAppendixAVerilogPrimer554brAIntroduction554brA2GeneralConceptsandModules554brA2ModuleStructure555brA22PortDeclarations556brA23DataTypes556brA24Numbers557brA3GateLevelStructuralModeling557brA3GateTypes557brA32GateDelays557brA4DataflowModeling558brA4ExpressionsOperandsandOperators558brA42ContinuousAssignmentStatements558brA43ContinuousAssignmentStatementDelay558brA5BehavioralModeling560brA5ProceduralBlocks560brA52ProceduralAssignments56brA53TimingControl562brA54caseStatements563brA55ifelseStatements563brA56LoopStatements565brA57BlockExecution566brA6HierarchicalModeling567brA6FunctionsandTasks567brA62StructuralModels568brA7SystemTasksandCompilerDirectives569brA8TestBenches570brA9SummaryofFeatures57brReferences572brAppendixBVHDLPrimer573brBIntroduction573brB2DesignUnitStructure574brB2SignalsandDataTypes574brB22OperatorsandExpressions579brB23DesignEntities580brB24DesignArchitectures583brB3BehavioralandDataflowModels583brB3ConcurrentSignalAssignments583brB32SignalDelays584brB33ConditionalSignalAssignments585brB34SelectedSignalAssignments586brB4StructuralandHierarchicalModels587brB4ComponentDeclaration587brB42ComponentInstantiation588brB5MixedModelingStyles590brB6ModelingSequentialBehavioral59brB6ProcessConstruct59brB62SequentialStatements592brB63SequentialCircuitModels594brB64SynchronousandAsynchronousControlSignals596brB65FiniteStateMachineModels597brB66RegisterTransferLevelRTLDesign598brB7SubprogramsPackagesandLibraries600brB7FunctionsandProcedures600brB72PackagesandLibraries602brB8TestBenches604brB9SummaryofFeaturesandKeywords607brReferences609br  內容待完善  (美)維克多·P.納爾遜 等 著 
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