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出版社:機械工業
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ISBN:9787111364580
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作者:(美)亨尼西
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頁數:856
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出版日期:2012-01-01
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印刷日期:2012-01-01
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包裝:平裝
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開本:16開
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版次:1
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印次:1
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《計算機體繫結構(量化研究方法英文版第5版)》堪稱計算機繫統結構學科的“聖經”,是計算機設計領域學生和實踐者的**經典。本書繫統地介紹了計算機繫統的設計基礎、存儲器層次結構設計、指令級並行及其開發、數據級並行、GPU體繫結構、線程級並行和倉庫級計算機等。 全書內容豐富,既介紹了當今計算機體繫結構的*新研究成果,也引述了許多計算機繫統設計開發方面的實踐經驗。 本書由斯坦福大學校長John L.Hennessy和加州大學伯克利分校計算機科學繫主任David A.Patterson等著。
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《計算機體繫結構(量化研究方法英文版第5版)》堪稱計算機繫統結構
學科的“聖經”,是計算機設計領域學生和實踐者的必讀經典。本書繫統
地介紹了計算機繫統的設計基礎、存儲器層次結構設計、指令級並行及其
開發、數據級並行、GPU體繫結構、線程級並行和倉庫級計算機等。
現今計算機界處於變革之中:移動客戶端和雲計算正在成為驅動程序
設計和硬件創新的主流範型。因此在這個最新版中,作者考慮到這個巨大
的變化,重點關注了新的平臺(個人移動設備和倉庫級計算機)和新的體繫
結構(多核和GPU),不僅介紹了移動計算和雲計算等新內容,還討論了成本
、性能、功耗、可靠性等設計要素。每章都有兩個真實例子,一個來源於
手機,另一個來源於數據中心,以反映計算機界正在發生的革命性變革。
《計算機體繫結構(量化研究方法英文版第5版)》內容豐富,既介紹了
當今計算機體繫結構的最新研究成果,也引述了許多計算機繫統設計開發
方面的實踐經驗。另外,各章結尾還附有大量的習題和參考文獻。本書既
可以作為高等院校計算機專業高年級本科生和研究生學習“計算機體繫結
構”課程的教材或參考書,也可供與計算機相關的專業人士學習參考。本
書由斯坦福大學校長John L.Hennessy和加州大學伯克利分校計算機科學繫
主任David A.Patterson等著。
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Foreword Preface Acknowledgments Chapter 1 Fundamentals of Quantitative Design and Analysis 1.1 Introduction 1.2 Classes of Computers 1.3 Defining Computer Architecture 1.4 Trends in Technology 1.5 Trends in Power and Energy in Integrated Circuits 1.6 Trendsin Cost 1.7 Dependability 1.8 Measuring, Reporting, and Summarizing Performance 1.9 Quantitative Principles of Computer Design 1.10 Putting It All Together: Performance, Price, and Power 1.11 Fallacies and Pitfalls 1.12 Concluding Remarks 1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin Chapter 2 Memory Hierarchy Design 2.1 Introduction 2.2 Ten Advanced Optimizations of Cache Performance 2.3 Memory Technology and Optimizations 2.4 Protection: Virtual Memory and Virtual Machines 2.5 Crosscutting Issues: The Design of Memory Hierarchies 2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-A8 and Intel Core i7 2.7 Fallacies and Pitfalls 2.8 Concluding Remarks: Looking Ahead 2.9 Historical Perspective and References Case Studies and Exercises by Norman R Jouppi,Naveen Muralimanohar, and Sheng Li Chapter 3 Instruction-Level Parallelism and Its Exploitation 3.1 Instruction-Level Parallelism: Concepts and Challenges 3.2 Basic Compiler Techniques for Exposing ILP 3.3 Reducing Branch Costs with Advanced Branch Prediction 3.4 Overcoming Data Hazards with Dynamic Scheduling 3.5 Dynamic Scheduling: Examples and the Algorithm 3.6 Hardware-Based Speculation 3.7 Exploiting ILP Using Multiple Issue and Static Scheduling 3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation 3.9 Advanced Techniques for Instruction Delivery and Speculation 3.10 Studies of the Limitations oflLP 3.11 Cross-Cutting Issues: ILP Approaches and the Memory System 3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput 3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-A8 3.14 Fallacies and Pitfalls 3.15 Concluding Remarks: What's Ahead? 3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R Colwell Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures 4.1 Introduction 4.2 Vector Architecture 4.3 SIMD Instruction Set Extensions fo.r Multimedia 4.4 Graphics Processing Units 4.5 Detecting and Enhancing Loop-Level Parallelism 4.6 Crosscutting Issues 4.7 Putting It All Together: Mobile versus Server GPUs and Tesla versus Core 4.8 Fallacies and Pitfalls 4.9 Concluding Remarks 4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos Chapter 5 Thread-Level Parallelism 5.1 Introduction 5.2 Centralized Shared-Memory Architectures 5.3 Performance of Symmetric Shared-Memory Multiprocessors 5.4 Distributed Shared-Memory and Directory-Based Coherence 5.5 Synchronization: The Basics 5.6 Models of Memory Consistency: An Introduction 5.7 Crosscutting Issues 5.8 Putting It All Together: Multicore Processors and Their Performance 5.9 Fallacies and Pitfalls 5.10 Concluding Remarks 5.11 Historical Perspectives and References Case Studies and Exercises by Amr Zaky and David A. Wood Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism 6.1 Introduction 6.2 Programming Models and Workloads for Warehouse-Scale Computers 6.3 Computer ArchitectureofWarehouse-Scale Computers 6.4 Physical Infrastructure and Costs of Warehouse-Scale Computers 6.5 Cloud Computing: The Return of Utility Computing 6.6 Crosscutting Issues 6.7 Putting It All Together: A Google Warehouse-Scale Computer 6.8 Fallacies and Pitfalls 6.9 Concluding Remarks 6.10 Historical Perspectives and References Case Studies and Exercises by Parthasarathy Ranganathan Appendix A Instruction Set Principles A.1 Introduction A.2 Classifying Instruction Set Architectures A.3 Memory Addressing A.4 Typeand Size of Operands A.5 Operations in the Instruction Set A.6 Instructions for Control Flow A.7 Encoding an Instruction Set A.8 Crosscutting Issues: The Role of Compilers A.9 Putting It All Together: The MIPS Architecture A.IO Fallacies and Pitfalls A.11 Concluding Remarks A.12 Historical Perspective and References Exercises by Gregory D. Peterson Appendix B Review of Memory Hierarchy B.1 Introduction B.2 Cache Performance B.3 Six Basic Cache Optimizations B.4 Virtual Memory B.5 Protection and Examples of Virtual Memory B.6 Fallacies and Pitfalls B.7 Concluding Remarks B.8 Historical Perspective and References Exercises by Amr Zaky Appendix C Pipelining: Basic and Intermediate Concepts C.1 Introduction C.2 The Major Hurdle of Pipelining--Pipeline Hazards C.3 How Is Pipelining Implemented? C.4 What Makes Pipelining Hard to Implement? C.5 Extending the MIPS Pipeline to Handle Muir/cycle Operations C.6 Putting It All Together: The MIPS R4000 Pipeline C.7 Crosscutting Issues C.8 Fallacies and Pitfalls C.9 Concluding Remarks C.10 Historical Perspective and References Updated Exercises by Diana Franklin Online Appendices Appendix D Storage Systems Appendix E Embedded Systems By Thomas M. Conte Appendix F Interconnection Networks Revised by -timothy M. Pinkston and Jos~ Duato Appendix G Vector Processors in More Depth Revised by Krste Asanovic Appendix H Hardware and Software for VLIW and EPiC Appendix I Large-Scale Multiprocessors and Scientific Applications Appendix J Computer Arithmetic by David Goldberg Appendix K Survey of Instruction Set Architectures Appendix L Historical Perspectives and References References Index
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